The present invention relates generally to a semiconductor memory device and more specifically to a semiconductor memory device, such as a DRAM (dynamic random access memory) having a self refresh mode and an externally applied exit command.
A dynamic random access memory (DRAM) includes memory cells for storing data. In order to prevent data loss, the memory cells must be refreshed within a specified time period. One mode of operation of a DRAM is a self refresh mode. When a self refresh mode command is executed, data stored in the memory cells is automatically refreshed while the DRAM is in a standby state. In the standby state, the system (such as a computer system in which the DRAM is included) may be excluded from accessing the DRAM. During the operation of the self refresh mode, the system is not reading from or writing data to the DRAM, thus, it is desirable to reduce power consumption by disabling unused circuitry on the DRAM.
Referring now to FIG. 3, a circuit schematic diagram of a portion of a conventional semiconductor memory device is set forth. The portion of a conventional semiconductor device of FIG. 3 is disclosed in Japanese Laid-Open Patent Publication No. Hei-7-65574 (JP 07065574 A). The conventional semiconductor device is a synchronous DRAM.
The portion of a conventional semiconductor memory device includes initial stage circuits (1 to 3), refresh command decision circuit 4, self refresh mode decision circuit 5 and an inverter 6.
Initial stage decision circuit 1 receives a self refresh latch signal SRS, a reference voltage Vref and an external clock ECK and provides an internal clock ICLK. Initial stage decision circuit 2 receives self refresh latch signal SRS, reference voltage Vref and a clock enable signal CKE and provides signal S1. Initial stage decision circuit 3 receives self refresh latch signal SRS, clock enable signal CKE and provides signal S2. Refresh command decision circuit 4 receives internal clock ICLK and external signals (/RAS, /CAS, /WE, and /CS) and provides a refresh command signal RC. Self refresh mode decision circuit 5 receives internal clock ICK, signal S1, and signal S2 and provides a signal S3. Inverter 6 receives signal S3 and provides self refresh latch signal SRS.
Initial stage circuit 1 includes a current mirror type receiver and is enabled when self refresh status latch signal SRS is at a low logic level. The initial stage circuit 1 outputs internal clock ICK. Internal clock ICK is a clock used in the conventional semiconductor memory device and is derived from external clock ECK. External clock ECK is a reference clock provided on the system.
Initial stage circuit 2 includes a current mirror type receiver and is enabled when self refresh status latch signal SRS is at the low logic level. Initial stage circuit 2 detects the logic level of clock enable signal CKE. The logic level of clock enable signal CKE determines whether or not external clock signal ECK is valid. When clock enable signal CKE is high and refresh status latch is low, initial stage circuit 2 provides signal S1 having a high level. However, when clock enable signal CKE is low, initial stage circuit 2 provides signal S1 having a low level.
Initial stage circuit 3 includes a complementary logic gate and is enabled when self refresh status latch is at the high logic level. Initial stage circuit 3 detects the release (exit) of the self refresh mode. The self refresh mode is exited when clock enable signal CKE transitions from the low logic level to the high logic level. In this case, initial stage circuit 3 provides signal S2 having a low level.
Refresh command decision circuit 4 detects an externally applied refresh command. The refresh command is provided by a low level row address strobe signal /RAS, a low level column address strobe signal /CAS, a low level chip select signal /CE, and a high level write enable signal /WE in synchronism with the rising edge of internal clock ICLK. Prefix xe2x80x9c/xe2x80x9d indicates negative logic. When a refresh command is detected, refresh command decision circuit 4 provides a refresh command signal RC having a high logic level.
Self refresh mode decision circuit 5 includes D-type flip-flop 7, D-type latch 8, NAND gate 9, and inverters (10, 11, and 12). When the refresh command signal RC indicates a refresh entry (set) to the self refresh mode, self refresh mode decision circuit 5 outputs signal S3 having a low logic level. Inverter 6 receives the low signal S3 and outputs self refresh latch signal SRS having a high logic level.
Referring now to FIG. 4, a timing diagram illustrating a conventional self refresh operation is set forth. The operation of the portion of the semiconductor memory device will now be described with reference to FIG. 4 in conjunction with FIG. 3.
Clock enable signal CKE is initially high before time t1 and transitions low at time t3. Also, because a refresh entry to the self refresh mode has not been executed, refresh command signal RC is low before time t3. Because refresh command signal RC is low, NAND gate 9 provides a high output as signal S3 from self refresh mode decision circuit 5. With signal S3 at the high level, inverter 6 provides a low output as self refresh latch signal SRS.
With self refresh latch signal SRS low, initial stage circuits (1 and 2) are in an enabled state and initial stage circuit 3 is in a disabled state. In this way, initial stage circuit 1 outputs internal clock ICK by delaying external clock ECK by a predetermined time as illustrated in FIG. 4. Initial stage circuit 2 receives the high clock enable signal CKE and outputs a high level signal S1. When in the disabled state, initial stage circuit 3 outputs a high level signal S2.
A refresh entry command is executed at time t3. This is done by providing clock enable signal CKE, row address strobe signal /RAS, column address strobe signal /CAS, and chip select signal /CS at a low level and write enable signal /WE at a high level at the rising edge of external clock ECK at time t3. Refresh command decision circuit 4 receives the refresh entry command and generates a refresh command signal RC having a high level in synchronism with internal clock ICK.
When clock enable signal CKE goes low, initial stage circuit 2 outputs signal S1 having a low level. After subsequent high and low transitions of internal clock ICLK, signal S1 propagates through D-type flip-flop 7 and D-type latch 8 to provide a signal S4 having a high level at time t4. With refresh command signal RC high and signal S4 high, NAND gate 9 provides a low signal S3 and inverter 6 provides self refresh status latch signal SRS having a high level after time t4.
With self refresh status latch signal SRS high, initial stage circuits (1 and 2) are disabled and initial stage circuit 3 is enabled. In this way, initial stage circuit 1 outputs internal clock ICK fixed at a high level regardless of the logic level of external clock ECK. Likewise, initial state circuit 2 outputs signal S1 having a low level. Because at this time clock enable signal CKE is kept low, initial stage circuit 3 provides signal S2 having a high level. By keeping ICLK high, self refresh mode decision circuit 5 keeps data latched in internal D-type flip-flop 7 and D-type latch 8 is not modified and the self refresh mode remains set. Thus, signal S4 is kept at the high level. Also, by keeping internal clock ICLK high, refresh command decision circuit 4 does not identify further applied commands and refresh command signal RC remains high as illustrated in FIG. 4.
Then, at around time t7, clock enable signal CKE transitions high. With clock enable signal CKE high, initial stage circuit 3 outputs signal S2 at a low level irrespective of the rising edge of external clock ECK. When signal S2 goes low, D-type latch 8 is reset to provide a high output and to cause signal S4 to go low. With signal S4 low, NAND gate 9 outputs signal S3 having a high level and inverter 6 outputs self refresh latch signal SRS having a low level. With self refresh latch signal SRS low, initial stage circuits (1 and 2) are enabled and initial stage circuit 3 is disabled. Thus, initial stage circuit 1 again generates internal clock ICK which is based on the external clock ECK delayed by a predetermined amount. Also, initial stage circuit 2 again outputs signal S2 having a high level in response to clock enable signal CKE having a high level.
In the same manner, refresh command decision circuit receives the signal S2 and is reset when signal S2 transitions low. Thus, refresh command signal RC transitions low at time t7 as illustrated in FIG. 4. In this way, the self refresh mode is exited.
In accordance with the example illustrated in FIGS. 3 and 4, when the mode of operation is set to the self refresh mode, initial circuits (1 and 2) are disabled. With initial circuits (1 and 2) disabled, their current consumption can be essentially zero. However, initial stage circuit 3 is enabled to provide a signal path to externally exit the self refresh mode. Initial stage circuit 3 is a complementary type input buffer. Thus, when clock enable signal CKE is provided having a sufficient voltage/logic level, such as a CMOS level of zero volts, the static current consumed by initial stage circuit 3 can be made to be essentially zero. In this way, the static current consumed by initial stage circuits (1 to 3) during the self refresh mode of operation can be essentially 0 mA.
In the conventional semiconductor memory device as described above, self refresh latch signal SRS changes to the low logic level to exit the self refresh mode in response to changing clock enable signal CKE from the low level to the high level.
The conventional semiconductor memory device illustrated in FIG. 3 can be susceptible to noise causing an erroneous logic level from clock enable signal CKE to be received by initial stage circuit 3. For example, as illustrated in FIG. 4 between times t5 and t6, a noise spike a is shown on clock enable signal CKE. If the noise spike a exceeds the threshold of the complementary input buffer within initial stage circuit 3, an unwanted logic transition may occur on signal S2. When such a noise spike is received after receiving the self refresh mode entry command, the self refresh mode may be erroneously exited. Such a situation may be caused, for example, just after the self refresh mode is set and a power supply in the system is interrupted in order to reduce system power consumption. This power supply interruption may cause noise on a device, such as a memory controller, supplying the clock enable signal CKE to the conventional semiconductor memory device.
Japanese Laid-Open Patent Publication No. Hei-10-125059, addresses this problem by disclosing a refresh mode having a refresh mode exit command. By using the refresh mode exit command the influence of the above-mentioned noise may be eliminated.
However, in Hei-10-125059, the setting and exiting (releasing) of the self refresh mode both executed with clock enable signal CKE in synchronism with external clock signal ECK. Accordingly, it is necessary to keep the initial stage circuit that generates internal clock ICK enabled during the operation of the self refresh mode. Thus, power consumption during the operation of the self refresh mode may be problematic.
In light of the above discussion, it would be desirable to provide a semiconductor memory device that may include a self refresh mode that may not be erroneously exited (released) due to the influence of noise or the like. It would also be desirable to provide the self refresh mode having a reduced power consumption.
A semiconductor memory device having a self refresh mode is disclosed. The self refresh mode may be entered in response to a self refresh set command and may be released in response to a self refresh release command. The self refresh release command may include a plurality of self refresh release commands sequentially executed while a clock enable signal is in a clock enable state. In this way, noise on a clock enable signal may not erroneously release the self refresh mode and the reliability of the self refresh mode may be improved.
According to one aspect of the embodiments, a semiconductor memory device may include a refresh operation entered upon the receipt of a refresh set command. The refresh operation may be released upon the receipt of a refresh release command wherein the release command may be executed over at least two cycles.
According to another aspect of the embodiments, the semiconductor memory device may be a synchronous dynamic random access memory and the at least two cycles may be two cycles of an external clock.
According to another aspect of the embodiments, the at least two cycles may be consecutive cycles of the external clock.
According to another aspect of the embodiments, the refresh release command includes a first refresh release command executed during a first cycle of the at least two cycles and a second refresh release command executed during a second cycle of the at least two cycles. The first refresh release command may include receiving a plurality of control signals having a first predetermined logic combination and the second refresh release command may include receiving the plurality of control signals having the first predetermined logic combination.
According to another aspect of the embodiments, the refresh release command include a first refresh release command executed during a first cycle of the at least two cycles and a second refresh release command executed during a second cycle of the at least two cycles. The first refresh release command may include receiving a plurality of control signals having a first predetermined logic combination and the second refresh release command may include receiving the plurality of control signals having a second predetermined logic combination.
According to another aspect of the embodiments, a first command decoder may be coupled to receive a plurality of external control signals and may generate a refresh set command signal based on the receipt of the refresh set command. A second command decoder may be coupled to receive a plurality of external control signals and may generate a refresh release command signal based on the receipt of the refresh release command.
According to another aspect of the embodiments, a semiconductor memory device may include a set signal output circuit coupled to receive a plurality of input signals. The set signal output circuit may provide a set signal that may set the operation of the semiconductor memory device to a refresh mode based on the plurality of input signals indicating a refresh set command. A release signal output circuit may be coupled to receive the plurality of input signals. The release signal output circuit may provide a release signal that releases the refresh mode based on the plurality of input signals indicating a refresh release command. The refresh release command may include a first refresh release command and a second refresh release command and the second refresh release command may be received after the first refresh release command. A status latch signal output circuit may be coupled to receive the set signal and the release signal. The status latch signal output circuit may provide a status latch signal indicating a refresh mode state. The refresh mode state may be set in response to the set signal and the refresh mode may be released in response to the reset signal. An enable circuit may be coupled to receive a clock enable signal and may provide an enable signal having a clock enable logic level and a clock disable logic level and may enable an internal clock to be generated based on an external clock when at the clock enable logic level. The release signal output circuit may be coupled to receive the clock enable signal and may be enabled to provide the release signal when the enable signal is at the clock enable logic level.
According to another aspect of the embodiments, the plurality of input signals may be any of a row address strobe signal, a column address strobe signal, a write enable signal, a chip select signal, addresses and data.
According to another aspect of the embodiments, the input signals may have a first logic combination indicating the refresh set command and a second logic combination indicating the first refresh release command.
According to another aspect of the embodiments, the enable circuit may be enabled when the status latch signal indicates the refresh mode state is set.
According to another aspect of the embodiments, the enable circuit may include a complementary logic gate input buffer.
According to another aspect of the embodiments, the status latch signal output circuit may include a reset-set (RS) flip-flop set in response to the set signal and reset in response to the release signal.
According to another aspect of the embodiments, the semiconductor memory device may be a dynamic random access memory and the refresh mode may be a self refresh mode.
According to another aspect of the embodiments, a semiconductor memory device may include a clock generator circuit coupled to receive an external clock and providing an internal clock. A set signal output circuit may be coupled to receive a plurality of input signals. The set signal output circuit may provide a set signal that may set the operation of the semiconductor memory device to a refresh mode based on the plurality of input signals received in synchronism with the internal clock indicating a refresh set command. A release signal output circuit may be coupled to receive the plurality of input signals. The release signal output circuit may provide a release signal that releases the refresh mode based on the plurality of input signals in synchronism with the internal clock indicating a refresh release command. The refresh release command may include a first refresh release command and a second refresh release command and the second refresh release command may be received after the first refresh release command. A status latch signal output circuit may be coupled to receive the set signal and the release signal. The status latch signal output circuit may provide a status latch signal indicating a refresh mode state. The refresh mode state may be set in response to the set signal and the refresh mode may be released in response to the reset signal. An enable circuit may be coupled to receive a clock enable signal and may provide an enable signal having a clock enable logic level and a clock disable logic level and may enable the internal clock to be generated based on an external clock when at the clock enable logic level. The release signal output circuit may be coupled to receive the clock enable signal and may be enabled to provide the release signal when the enable signal is at the clock enable logic level.
According to another aspect of the embodiments, the clock generator circuit may be disabled when the enable signal is in the clock disable logic level and the status latch signal indicates the refresh mode.
According to another aspect of the embodiments, the set signal output circuit may provide the set signal in synchronism with the internal clock and the release signal output circuit may provide the release signal in synchronism with the internal clock.
According to another aspect of the embodiments, the input signals may have a first logic combination indicating the refresh set command and a second logic combination indicating the first refresh release command.
According to another aspect of the embodiments, the enable circuit may be enabled when the status latch signal indicates the refresh mode state.
According to another aspect of the embodiments, the set signal output circuit and release signal output circuit may be coupled to receive a second internal clock based on the internal clock when the enable signal is in the clock enable logic level.
According to another aspect of the embodiments, the release signal output circuit may include n (n is a natural number) flip-flops and n logic circuits. Each logic circuit may be coupled to receive the plurality of input signals. Each one of the n logic circuits may provide an output coupled to an input of a respective one of the n flip flops which may be latched synchronously with the internal clock. The first flip-flop may provide an output coupled to an input of the second logic circuit and the (n-1) flip-flop may provide an output coupled to an input of the nth flip-flop. The output of the nth flip-flop may be coupled to provide the release signal.